The invention relates generally to semiconductor device fabrication and, in particular, to wiring paths used for signal communication in an integrated circuit, such as through silicon vias (TSVs) used in three-dimensional chip integrations to transfer signals vertically through the stacked chip architectures.
Three-dimensional integrated circuits with through silicon vias (TSVs) have emerged as a technique for supplying vertical interconnections in the semiconductor manufacturing industry. TSV technology is of interest, for example, in creating three-dimensional chip stacks. Stacking chips in a three-dimensional chip stack shortens signal transmission distances for chip-to-chip communications and promotes a large increase in the number of inter-chip links. The improvement in electrical performance provided by a three-dimensional chip stack strongly depends on the fidelity of signal transmission through the TSVs. Because the TSV formation process is imperfect, defective TSVs can be created either before or during chip bonding. A defective TSV may have an abnormally high electrical resistance that degrades signal quality or that opens a signal path.
Despite the success of TSVs and other types of wiring paths for their intended purpose, methods and systems are needed for repairing defective wiring paths, such as TSVs used in three-dimensional chip integrations, characterized by abnormally high electrical resistance.